A Serializer/DeSerializer (SerDes) is an important building block in high speed computer networks and data communications systems. In applications that use a SerDes, no clock is included in the transmission of data signals. Instead, a receiver must extract the timing information from a received data signal and establish a data clock which is used to re-time the received data. The function of extracting the timing information is fulfilled by a clock data recovery (CDR) circuit.
In SerDes applications, the data link channel in which data is transmitted (for example through a Printed Circuit Board (PCB) backplane) to the SerDes is usually highly lossy, highly dispersive and bandwidth limited. The channel loss is a strong function of the frequency at which the data is transmitted. This channel loss can result in the occurrence of errors from Inter-Symbol Interference (ISI) in the received data unless there is some form of compensation included in the SerDes.
The ISI of the signal link path can be approximately modeled as a linear system with finite memory. In mathematical terms, this is a finite state machine (FSM), where the system output signals are affected by signals that occur earlier and later in time. FIGS. 1A-1C show an example of the effect of ISI on a bipolar non-return-to-zero (NRZ) digital signal having a pulse width of 1 T (shown in FIG. 1A). FIG. 1A shows the original pulse. FIG. 1B shows the pulse after it has been affected by ISI. Particularly, the NZR signal is time stretched by ISI into an analog signal whose width is roughly 3 T. On an actual backplane, depending on trace length, material, layout, and signal data rate, the width of the distorted signal may extend to many times the one-bit duration of the digital signal and the dispersion may not be evenly distributed, i.e., the leading edge and falling edge may be affected differently. In general, such an ISI-distorted signal can be partitioned into 3 sections: a main cursor, a pre-cursor and a post-cursor. Finally, FIG. 1C shows a discrete signal model that digitally emulates the waveform of FIG. 1B.
Compensation for the channel loss in the data link channel is usually realized by means of equalization techniques on both the transmit side and the receive side of a SerDes. Equalization is a signal processing technique used to compensate the degrading effects of transmission paths. The equalization technique on the transmit side is often called transmitter pre-emphasis (TXPE) or de-emphasis, while that on the receive side is termed receiver equalization (RXEQ). High speed CDR and equalization blocks are typically made of analog and digital circuits that work with clock signal with frequencies in excess of 1 GHz.
The ability to track a certain amount of ISI by the CDR or remove some ISI by the RXEQ is critical to systems using SerDes. In the transmitter, a common equalization technique is to use a TPXE to apply pre-emphasis to boost the signal transitions and hence the higher frequency components, in order to compensate for the low frequency pass nature of the link path. FIG. 2A shows one example of a conventional implementation of a TXPE 200 used for pre-emphasis. An Input signal D0 is split into two signals. The first of the split signals is multiplied by a coefficient Cmain=2 in a main multiplier 204 main to generate a signal D2. The second of the split signals is delayed by one period (1 T) in a delay element 202 and then multiplied by a coefficient Cpost=−1 in a post-cursor multiplier 204 post (resulting in a delayed and inverted version of the input signal) to generate a signal D3. In practice, the values of the coefficients Cpost and Cmain may take on a wide range of values. The values of Cpost=−1 and Cmain=2 are chosen here for illustrative purposes. The multiplied signal D2 and the delayed and multiplied (inverted) signal D3 are input to a summing element 208. The output of the TXPE is the signal generated by the summer 208. FIG. 2B shows waveforms D0, D1, D2, D3 and Output that illustrate the function of the TXPE of FIG. 2A in response to an input signal having a pattern of four 1's and four 0's.
Since the CDR and CDR/RXEQ of a SerDes run at such high data rates, these circuit blocks are limited within an extremely tight timing budget and need to be stringently tested. However, as the data rate of the transmitted data increases beyond multi-gigabits-per-second (Gbps), conventional automated test equipment (ATE) methods of testing the integrity of CDR circuits and the effectiveness of equalization are ineffective.
Conventional ATE testing is inadequate for testing the performance of the CDR and the RXEQ of a conventional SerDes because traditional scan methods are either insufficient or not practicable. Only the amplitude (vertical) of a transmitter signal can be varied with conventional ATE testing, so the channel loss effects of the data link channel cannot be effectively modeled on the high speed, quasi-analog circuits of the CDR and the RXEQ. Due to the short and fixed length traces on ATE testers, signal smearing is minimal and constant for a given data rate. Additionally, implementing variable length traces on an ATE load board or in the ATE tester is not practical, especially when the device under test (DUT) contains dozens or even hundreds of channels. Thus, no meaningful horizontal timing closure is possible to fully test the CDR and the RXEQ blocks of the SerDes. From an eye diagram perspective, the horizontal eye opening is not stressed.
Currently the only way to fully screen the CDR and the RXEQ devices of a conventional SerDes is to use at-speed functional tests in a controlled lab environment, which employs expensive bit-error ratio testers (BERT), high bandwidth real time and sampling oscilloscopes, high speed signal generators, and various backplanes (model or real-world parts). However, this lab method is slow, involves expensive test equipment and requires constant supervision by experienced engineers. Thus, lab testing is not suitable for volume production testing.
If the CDR and the RXEQ devices are not rigorously tested, the devices may contain dormant defects that can deteriorate in the field. Such problems are very difficult to debug once they are in a system and the replacement cost is extremely high. Thus, when SerDes devices containing defects are shipped to customers, it can be very costly to replace them. As a result, there is a need for an efficient ATE-friendly test method to screen a SerDes device, especially the CDR circuits and the RXEQ functional blocks, before they are deployed.